Senior Physical Design Engineer

We offer you:

· Competitive Salary & Benefits;

· Respect for your private life and your choices;

· All tools required for high performance in your field;

· Responsible approach, long-term commitments and stability.

Desired qualifications/skills:

· 8+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k –1million+ instances in designs;

· Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence

· Good knowledge of synthesis flow, insertDFT scan/coverage and optimization

· Excellent floorplan, power plan, CTS, place, route, and timing closure skills;

· Proficiency using Perl/TCL/Python scripting and Makefile;

· Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;

· Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;

· Experience with sign-off tape-out closure work;

· Any top level – floor planning, pin assignment – tape out activities is a plus.

Your role:

· Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);

· In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;

· Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);

· In charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;

· Be part of the overall Low Power solution development and implementation;

· Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);

· Complete multiple design cycles of high complexity with little supervision